Magnetic relay reset system



Jan. 1961 J. G. PEARCE ETAL 2,968,749

MAGNETIC RELAY RESET SYSTEM Filed March 12, 1959 JAMES a. PEARCE //v vs/v TOPS: AN THO/V! a SOWERS au/vrm SAGE/P 8V FWM A 7 TORNE P States MAGNETIC RELAY RESET SYSTEM Filed Mar. 12, 1959, Ser. No. 799,009

5 Claims. (Cl. 317-148) This invention relates to switching systems and particularly to telecommunication means generally situated at a point distant from any considerable source of power whereby circuitselection and the release of established connections may be accomplished by low power pulse means.

The object of the invention is the provision of means for dismissing an established connection by pulse control applied in common to a plurality of circuit switching means while maintaining the level of power necessary for a resetting operation only very slightly above that necessary for a single such operation and for automatically limiting the application of such power to the minimum time required therefor.

The invention consists of the association with a conventional mechanically locking electromagnetically operated and electromagnetically released relay, a square loop memory element for signaling the operated or non-operated state of each said relay and certain semiconductor electronic devices responsive to poled pulses for generating current application to relay windings sufficiently powerful and of only sufiicient duration to cause the desired operation thereof.

A feature of the invention is the use of a common series path extending through a plurality of like circuits and having a unit in each said circuit consisting of an electromagnetic coil in parallel with an energizing coil wound about a core of square loop magnetic material. In such a unit circuit, if a direct current is passed therethrough in a direction which would result in the driving of such core to its opposite magnetic state, then during the magnetic transition thereof the impedance of such coil on the said core will be high and the current in the said series circuit will be almost wholly carried by the electromagnetic coil, but if the core is saturated in the other sense so that no transition of the magnetic state of the core may be brought about, then the impedance of the core coil will be very low as a consequence of which the impedance of this parallel circuit unit will be very low so that in the overall series circuit the current will be practically confined to that electromagnetic coil which is in parallel with the core being driven to its other state. This feature may therefore be stated to be a series circuit including a plurality of units each of which includes two parallel branches, one of which consists of a coil magnetically coupled with a square loop bistable magnetic element, the total impedance of said series circuit being low but which will respond to a current passed therethrough by greatly increasing the impedance of any one of said coils coupled with a said bistable magnetic element which had previously been driven to an opposite and active state to confine substantially all the series circuit current to its associated electromagnetic coil.

Another feature of the invention is the use in a switching device having a plurality of switching units of a bistable square loop magnetic memory element associated with each said switching device and having a coil atent Patented Jan. 17, 1961 connected in parallel with the said switching device, and each said bistable element having another coil for fortifying and prolonging the current passed through its first said coil whereby a triggering pulse used for operating said switching device may be maintained until the switching operation has been completed. More specifically, the said switching device consists of two coils one for setting said device and the other for resetting said device. Each said coil has an associated memory element coil which is responsive to current flowing in a different direction whereby the pulse generated by a third memory element coil is poled differently. These poled pulses are fed into a circuit having two outlets one for fortifying and maintaining a switching device setting pulse and the other for fortifying and maintaining a switchng device resetting pulse.

Another feature of the invention is the use of an individual input circuit for the said switching device setting coils and their coupled memory element coils and a common resetting circuit for the said switching device resetting coils and their coupled memory element coils whereby a resetting pulse transmitted for the specific purpose of resetting a particular switching device will guarantee the resetting of all the said switching devices.

Another feature of the invention resides in an electronic means for setting and for resetting magnetic relay devices by pulses each of a power and time duration insufficient in itself to produce the desired result. In accordance with this feature the incoming switching pulse is used to trigger a square loop bistable magnetic memory element which in response not only adjusts the impedance of the circuit of the relay device but maintains the original pulse until the object thereof is attained whereby the power for operating the said relay is prolonged sufiiciently for the purpose but where waste is avoided by the cutting off of said power upon the instant of completion of the operation.

Other features will appear hereinafter.

The drawing consists of a single sheet having a single figure in the form of a schematic circuit diagram showing the essential elements of the present invention but leaving many of the items of conventional circuitry not shown.

The drawing indicates the telecommunication switching means controlled by a plurality of electromagnetically operated mechanically locking and unlocking relays, R-1, R-2 and R-N each having a winding S for setting or moving the contact means thereof into its latched position and a separate winding R for unlatching and re1eas ing such contacts from their operated positions.

These relays may each be selectively operated by a positive going pulse applied to its individual incoming terminal X-l, X-2 or X-N. When such a positive pulse is applied to the terminal X-1, by way of example, the associated NPN transistor Q-l is placed in a conducting state through the S winding of its associated relay R-1 and in parallel therewith through the lower winding of its associated square loop memory device C-l. Since this core is normally in its binary 0 state wherefrom it will be driven to its binary 1 state by this current flow, a pulse will be generated in the right hand transformer coupled winding of the core C-l. This pulse will find a path through the diode D-l, thence through the conventional amplifier A-l to fortify the pulse applied to the terminal X-1 and to maintain the transistor Q-1 in conduction until the operation of the core C-1 has been completed.

Through proper engineering arrangements, the time required for the saturation of the core C-I is made longer than the time required for the operation of the relay, whereby the time of the pulse applied to the incoming terminal X-l may be only long enough for a triggering operation and not necessarily long enough for the operation of the relay. Since the impedance of the branch of this core setting circuit is high during this setting operation, the current through the parallel branch through the winding S of the relay will be comparatively low and hence a heavy current will flow through the relay winding. As soon as the core is set, however, most of the current will flow through the core winding and very little will flow through the relay but this being a steady state flow the current through the right hand winding of the core and thence through the diode D-l, the amplifier A4 and the emitter of Q-l will drop off to zero and the transistor Q-l will cease to conduct.

It will thus appear that there will be one .of a chain of N cores and N relays in theset condition. After the desired use of the operated and latched relay has been terminated it may be desired to guarantee that all of these are reset. This may be accomplished by applying a positive pulse to the common reset terminal Y to drive the transistor Q-4 into conduction.

The current now flowing into the collector of (1-4 and thence out of the emitter thereof, fiows through a chain circuit starting at a source of positive potential at the first circuit and within that circuit dividing into two parallel paths, one through a diode E-ll and the reset coil of the relay R1 and the other through the left hand coil of the core C-l. All the cores which have not been set (to their binary 1 condition) will be saturated in this reset condition and will thus offer an extremely low impedance to this current and will consequently substantially short circuit their associated reset relay windings. However, in the case of the core and the relay which has been set, this core will offer a high impedance to the current and most of the current will then flow through the relay coil. In this manner, the relay which is set will absorb the reset power and will be reset by this.

At the same time, the core which is being reset will be sending out a signal over its right hand winding toward the diode D1 but this Will be of the opposite polarity so that it will be barred from the amplifier A-l but will be admitted through the diode F-l to the inverter amplifier I to place a positive pulse on the terminal Y and thus fortify the reset pulse and maintain it until the core C1 has been completely reset to its binary condition. This makes it possible to use a short duration or triggering pulse applied to the terminal Y for reset purposes. The cores in this arrangement are used both to remember the state of each relay and to steer the reset pulse accordingly, and, to time the set and reset pulse. In each case it is necessary that the time for saturation of the core due to either a set or reset pulse must be longer than the maximum time required by the relay for its set or reset operation. The advantage of this circuit over one in which a mass reset pulse is applied to all relays is that it is only necessary to drive one relay and the series direct current impedance of the remaining cores, whereas if the more conventional means is employed, N times the power is required.

What is claimed is:

1. In a switching device, a plurality of electromagnetically operated switching units, individual means for each said unit for transmitting se ting pulses, a means common to all said units for transmitting resetting pulses, each said unit having a setting coil and a resetting coil and an individual bistable square loop magnetic memory element associated therewith, a first coil interlinked with said memory element and connected to said setting coil, a second coil interlinked with said memory element and connected to said resetting coil and a third coil interlinked with said memory element and responsive to both said individual setting pulse and said common resetting pulse for fortifying and maintaining the said setting and the said resetting pulses transmitted to said setting and said 'reseting coils and their connected memory element coils through transformer cooperative relationship between said third memory element coil and said first and said second memory element coils respectively.

2. In a switching device, a plurality of electromagnetically operated switching units, individual means for each said unit for transmitting setting pulses, a means common to all said units for transmitting resetting pulses, each said unit having a setting coil and a resetting coil and an individual bistable square loop magnetic memory element associated therewith, a first coil interlinked with said memory element and connected to said setting coil, a second coil interlinked with said memory element and connected to said resetting coil and a third coil interlinked with said memory element and responsive to both said individual setting pulse and said common resetting pulse for fortifying and maintaining the saidsetting and the said resetting pulses transmitted to said setting and said resetting coils and their connected memory element coils through transformer cooperative relationship between said third memory element coil and said first and saidsecond memory element coils respectively, said resetting coil and its said associated memory element coil being connected in parallel to each other, the impedance of said memory element coil being normally of a value low enough to substantially shortcircuit its said associated resetting coil, said memory element being subject to a change in state when in a set condition responsive to a prior transmission of a setting pulse whereby on the transmission of a resetting pulse said second memory element coil responsive to said change in state will become of high impedance to divert current in said resetting circuit substantially all through said associated resetting coil.

3. In a switching device, a plurality of electromagnetically operated switching units, individual means for each said unit for transmitting setting pulses, a means common to all said units for transmitting resetting pulses, each said unit having a setting coil and a resetting coil and an individual bistable square loop magnetic memory element associated therewith, a first coil interlinked with said memory element and connected to said setting coil, a second coil interlinked with said memory element and connected to said resetting coil and a third coil interlinked with said memory element and responsive to both said individual setting pulse and said common resetting pulse for fortifying and maintaining the said setting and the said resetting pulses transmitted to said setting said resetting coils and their connected memory clement coils through transformer cooperative relation. ip tween said third memory element coil and said first and said second memory element coils respectively, said resetting coil and its said associated memory element coil being connected in parallel to each other and said assooiated parallel connected pairs of resetting coils and memory element coils being connected in seriesand presenting a low impedance series circuit; the impedance of said memory element coil being normally of a value low enough to substantially shortcircuit its said associated resetting coil, said memory element being subject to a change in state when in a set condition responsive to a prior transmission of a setting pulse, whereby on the transmission of a resetting pulse said second memory element coil of that series combination having a said set memory element in response to said resulting change in state will become of high impedance to divert substantially all the resetting pulse current in said series circuit into said associated resetting coil.

4. In a switching device, a plurality of electromagnetically operated switching units, individual means for each said unit for transmitting setting pulses, a means common to all said units for transmitting resetting pulses. each said unit having a setting coil and a resetting coil and an individual bistable square'loop magnetic memory element associated therewith, a first coil interlinked with said memory element and connected to said setting coil, 21 seeond'coil interlinked with said memory element and connected to said resetting coil and a third coil interlinked with said memory element and responsive to both said individual setting pulse and said common resetting pulse for fortifying and maintaining the said setting and the said resetting pulses transmitted to said setting and said resetting coils and their connected memory element coils through transformer cooperative relationship between said third memory element coil and said first and said second memory element coils respectively, said resetting coil and its said associated memory element coil being connected in parallel to each other and said associated parallel connected pairs of resetting coils and memory element coils being connected in series and presenting a low impedance series circuit, the impedance of said memory element coil being normally of a value low enough to substantially shortcircuit its said associated resetting coil, said memory element being subject to a change in state when in a set condition responsive to a prior transmission of a setting pulse, whereby on the transmission of a resetting pulse said second memory element coil of that series combination having a said set memory element in response to said resulting change in state will become of high impedance to divert substantially all the resetting pulse current in said series circuit into said associated resetting coil, said individual means for each said unit for transmitting setting pulses including a semi-conductor device responsive to an incoming pulse to trigger a change in state of said memory element, said semi-conductor device being responsive to a pulse created in said third coil of said memory element by said change in state to fortify and prolong said setting trigger pulse over a period suflicient to operate said associated setting coil.

5. In a switching device, a plurality of electromagnetically operated switching units, individual means for each said unit for transmitting setting pulses, a means common to all said units for transmitting resetting pulses, each said unit having a setting coil and a resetting coil and an individual bistable square loop magnetic memory element associated therewith, a first coil interlinked with said memory element and connected to said setting coil, a second coil interlinked with said memory element and connected to said resetting coil and a third coil interlinked with said memory element and responsive to both said individual setting pulse and said common resetting pulse for fortifying and maintaining the said setting and the said resetting pulses transmitted to said setting and said resetting coils and their connected memory element coils through transformer cooperative relationship between said third memory element coil and said first and said second memory element coils respectively, said resetting coil and its said associated memory element coil being connected in parallel to each other and said associated parallel connected pairs of resetting coils and memory element coils being connected in series and presenting a low impedance series circuit, the impedance of said memory element coil being normally of a value low enough to substantially shortcircuit its said associated resetting coil, said memory element being subject to a change in state when in a set condition responsive to a prior transmission of a setting pulse, whereby on the transmission of a resetting pulse said second memory element coil of that series combination having a said set memory element in response to said resulting change in state will become of high impedance to divert substantially all the resetting pulse current in said series circuit into said associated reset coil, said individual means for each said unit for transmitting setting pulses including a semi-conductor device responsive to an incoming pulse to trigger a change in state of said memory element, said semi-conductor device being responsive to a pulse created in said third coil of said memory element by said change in state to fortify and prolong said setting trigger pulse over a period sufiicient to operate said associated setting coil, said common means for transmitting resetting pulses including a semi-conductor device responsive to an incoming pulse to trigger a change in state of a previously set memory element, said last semi-conductor element being responsive to a pulse created in any one of said third coils of said memory elements by a change in state from a set to a reset condition to fortify and prolong said resetting trigger pulse over a period suflicient to operate said associated resetting coil.

References Cited in the file of this patent UNITED STATES PATENTS 

